Dynamic circuits have achieved widespread use because they require less silicon area and have superior performance over conventional static circuits. Unlike static circuits, dynamic circuits store data in the form of charge that dissipates in a short period of time due to leakage current. Consequently, dynamic circuits must periodically refresh the charge in order to properly retain data. A well-known dynamic circuit is a dynamic random access memory (DRAM) that stores data on charged capacitors.
Dynamic circuits can also be used to implement logic functions. An example of a dynamic logic circuit is shown in FIG. 1A, where a four-input logic function is implemented. A circuit 100 includes a precharge transistor 112 tied to power (Vdd), an evaluation transistor 114 tied to ground and a logic block 116 (shown in dashed lines) coupled between the precharge and evaluation transistors. Logic block 116 has a group of three input transistors 118, 120, 121 coupled in series and one input transistor 122 coupled in parallel across the other input transistors. A clock signal path 123 is coupled to the precharge and evaluation transistors.
FIG. 1B shows a waveform of a clock signal on the path 123. The signal has precharge And evaluation portions in its clock cycle which correspond to precharge and evaluation phases of the circuit. During the precharge phase, transistor 112 is activated (operating in saturation), charging a precharge node 124 and the logic block 116 to a logic high voltage level. Conversely, transistor 114 is inactive (substantially turned off) during the precharge phase. With precharge node 124 at a high voltage level, a primary output 126 is at a logic low voltage level because inverting buffer 128 inverts the output of node 124.
During the evaluation phase, the evaluation transistor 114 is active and the precharge transistor is inactive. If each serially coupled input transistor 118, 120, 121 in logic block 116 is activated or if input transistor 122 is activated, then the logic block is said to be "conducting" (substantially a short circuit), and the evaluation transistor pulls the precharge node 124 and the logic block 116 low. Otherwise, the precharge node and the logic block remain at their precharged level.
Each transistor in the logic block has an associated capacitance (not shown). The precharge transistor 112 must be large enough to charge all of the transistors in the logic block 16 during the precharge phase. If the precharge transistor is too small, the capacitance of the transistors in the logic block may absorb enough charge to prevent the voltage on node 124 from rising to a high voltage level.
The more sophisticated the circuit, the more input transistors are needed in the logic block, and the larger the precharge transistor must be in order to overcome the capacitance of the logic block. Increasing the size of the precharge transistor increases the area and power used by the circuit. Moreover, increasing capacitance of the logic block increases the propagation delay (i.e., slows the speed) of the circuit. The speed of the circuit is determined by how fast the evaluation transistor can remove charge from the precharged logic block and the precharge node. The more inputs in the logic block, the greater the charge that the evaluation transistor must remove, and, hence the slower the circuit. Thus, power, area and speed are all related to the number of inputs to the circuit. The greater the number of inputs, the greater the amount of power needed to run the circuit, the greater the area the circuit uses, and the greater the circuit's propagation delay.
Using the circuit of FIG. 1, designers must weigh the advantages of including new features into a circuit against the increase in power, area and propagation delay as a result of the new features.
It is, therefore, desirable to have a circuit that has constant power and propagation delay regardless of the number of inputs to the dynamic logic block.
FIG. 2 shows a known dynamic logic circuit that attempts to overcome the problems of the FIG. 1 circuit. A precharge transistor 200 is isolated from a logic block 202 by an evaluation transistor 204. Each transistor T.sub.0 -T.sub.4 in the logic block 202 has an associated capacitance that is represented by capacitors C.sub.0 -C.sub.4. A precharge node 206 also has capacitance associated with it as represented by a capacitor C.sub.5. Unlike FIG. 1, the precharge transistor 200 does not charge the logic block 202 to an appropriate high voltage level during the precharge phase. Instead, the evaluation transistor 204 is off during the precharge phase, isolating the precharge transistor from the logic block. The precharge transistor of FIG. 2 may be smaller, consequently, than the precharge transistor in the circuit of FIG. 1, thereby saving power and area.
Nonetheless, the circuit of FIG. 2 is generally considered a poor design because charge-sharing between the logic block and the precharge node during the evaluation phase can cause the precharge node to undesirably go low. See Principles of CMOS VLSI Design: A System Perspective, 2nd Edition, by Neil Weste and Kamran Eshraghian, FIG. 5.37(a). For example, assume the inputs I.sub.1 -I.sub.4 are high (transistors T.sub.1 -T.sub.4 are active), while input I.sub.0 is low (transistor T.sub.0 is inactive). When the evaluation phase begins, all of the charge associated with capacitor C.sub.5 (stored during the precharge phase) is shared with capacitors C.sub.1 -C.sub.4 because the elevation transistor allows current to flow therebetween. Given the inputs, the output is supposed to be a logic low (since T.sub.0 is inactive). Instead, the capacitors C.sub.1 -C.sub.4 absorb enough charge from capacitor C.sub.5 that the circuit output erroneously goes high. The larger the number of inputs, the more charge-sharing that occurs and the more likely the circuit will improperly operate.
An objective of the invention, therefore, is to provide an improved dynamic logic circuit that overcomes the deficiencies of the prior art.